1 BCM datasheet errata. the BCM Broadcom specifies the reserved bits the other way around: “Write zeroes, read: don’t care”. Read about ‘Broadcom: Datasheet for BCM ARM Peripherals’ on element14 .com. Broadcom: Datasheet for BCM ARM Peripherals. If you have been following Raspberry Pi project, you may have noticed the dearth of documentation related to Broadcom processors.

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Two bits high would be consistent with TX empty and RX empty. I strongly suspect that the CDIV counter is only 14 bits wide. Therefore, the dstasheet of this small test application project is to:. Many datasheets specify “write: If 0 the receiver shift register is cleared before each transaction. An easy implementation would implement the 0 value as the maximum divisor. The mashing dividers are build such that clock artifacts should be pushed out of the audio frequency domain.

This is not true. Not really an erratum, but not worth it to make a whole page for this. Allusions to the APB clock domain are made. This is confusing as indeed there is a different module called SPI0 documented on page and onwards.

Raspberry Pi Releases BCM2835 Datasheet for ARM Peripherals

In table the values in columns “min output freq” and “max output freq” should be in each others. It looks like it contains the information that programmers need. They should both read “If this bit cleared no new symbols will be Introduction This test application is intended to present a simple to understand user space test application that can be used to control the output of the Raspberry PI I2S bus.


There is a space in ” full ” that would hint at that the word “half” was taken away. The way it is written now, this bit is just the same as bit RXF, except that the TA bit is anded into this one. Instead of “when all register contents is lost. This may happen every time this bit is set, but it is not measurable every time when sampling at 16MHz higher sampling speeds would be needed to confirm that. If 1 the receiver shift register is NOT cleared.

Does this mean, that the SYNC bit can also be changed at runtime as well?

Views Read View source View history. The bottom bit doesn’t work as per specifications, and because the “0” results inthe top bit doesn’t either. The register dataseet as 0x after reset. This shows a bit pattern of as alternative function 3. Link to it via two control blocks on the primary chain. The divider is split between an integer divider and a fractional mashing divider.

You must write the MS 8 bits as 0x5A. The CDIV value is documented as “must be a power of 2”.

I think- not confirmed. Privacy policy About eLinux. This page was last edited on 9 Julyat If you follow the datasheet, and write zeroes as specified to the reserved bits, the hardware guys can make sure you’re not going to run into surprises.

Retrieved from ” https: There is a bug in the I2C master that it does not support clock stretching at arbitrary points.

UART 1 should be: It also “does the right thing” with reserved bits. Or the hardware does what I expect: However the exact speed of the APB clock is never explained.


Navigation menu Personal tools Log in Request account. This bit would be useful if it signified more than half full. Another hint is that it says that the bit clears when “sufficient” data is read from the FIFO. If 1 the data is shifted in starting with the MS bit. The IO register is documented as 0x7ea0 with automatic deassert and 0x7eb0, whereas the table on page 8 shows 0x7e This does not match the diagram on page – which shows this function is selected with alternative function 4.

However, bits 7 and 9 does not match the original datasheet, nor my guess If you expand the hardware the hardware may be enhanced and do “different things” if you write ones to the previously “reserved” bits. This is from Geert Van Loos at the page below:. There is amiguity on what register bits can be modified while the I2S system is active.

BCM Datasheet(PDF) – Broadcom Corporation.

The hardware was changed detecting “half full” was difficult? This had lead to a confusing picture. The I2C section on page 34 mentions MHz as a “nominal core clock”.

The Peek register is documented here as being at 0x7ec, whereas the table on page 8 shows 0x7e The table, legend for tablestarted on page shows twice in red: Near the bottom of the page RXR.