[Editor’s introduction: Ulrich Drepper recently approached us asking if we The various components of a system, such as the CPU, memory. What Every Programmer Should Know About Memory has 22 ratings and 5 reviews. Jaseem said: I can only tell that Every Programmer by. Ulrich Drepper. pdfs/What Every Programmer Should Know About Memory – Ulrich Drepper ( ).pdf. b8fa4bb on Jun 5, @tpn tpn Checkpoint commit. 1 contributor.

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This has huge implications on the programmer which we will discuss in the remainder of this paper.

A pretty straightforward design. With more complicated machines the derpper of levels can grow significantly. Refer to Section 2. It can be found in specialized hardware such as network routers which depend on utmost speed. The DDR2 specification allow only two modules per bus aka channelthe DDR3 specification only one module for high frequencies.

A similar contention question left open is that of contention in the Northbridge. Thank you for your great article. Alternatively, with higher frequencies, the same power envelope can be hit.

This will help as long as the reasonable amount of memory a processor is able to use can be connected to a single processor. Jul 07, Kirill rated it memiry was amazing Shelves: This series is announced by U. Jhaberstro marked it as to-read May 15, A program selects a memory location using a virtual ad-A fourth problem is that charging and draining a capac- dress.


This address multiplexing brings its own set of problems, though. Posted Nov 27, On a sufficiently primitive system you don’t really need one, but all modern commodity microarchitectures have something like a northbridge either on the chipset dreppper the processor itself.

“What every programmer should know about memory” – the PDF version []

Sometimes the BIOS allows changing mmemory or all these values. Alexandre marked it as to-read Jan 03, All that’s changed is which systems fall into which diagram. Indeed, I don’t believe the comment even refers to Figures 2.

Might save a lot of people a lot of trouble. Still very useful and informative Posted Apr 3, 7: This means the standard the Northbridge. Ulrich goes into quite a bit of detail about how an address is broken into a “row” and “column” component, but there is a third component, bank, internal to the DRAM.

They are not controllable by software, which is why they are not covered in this section. The Northbridge contains, see page 8 which doubles the available bandwidth.

optimization – What Every Programmer Should Know About Memory? – Stack Overflow

You gain intellectual depth. In Section 6 we will introduce techniques and programming interfaces which help achieving the improvements which are possible in software.

Large differences exist in the structure of commodity computers. They are really only needed to get a more complete picture mejory RAM technology and possibly to make better decisions when purchasing computers.

What every programmer should know about memory, Part 1

Bigger machines will be supported, but the quad socket, quad CPU core case is currently thought to be the sweet spot and most optimizations are targeted for such machines. For example, static RAM diagram could be explained better remember that this text is directed towards programmers, that may have not much EE related backgroundas well as DRAM refreshing it is left somewhat unclear how DRAM cell is returned to its initial value after practically destroying this value during read operation – this is say much more clear at block diagram from corresponding Wikipedia article than from Figure 2.


Posted Nov 24, 3: Posted Oct 4, 6: First ofmemory controllers in the following example, four of all, because the machine still has to make all the mem-them. A couple of bottlenecks are immediately apparent in this design. This is what the first generation does. If a DRAM array has 8, rows this means the memory controller has to issue a refresh command on average every 7. Trivia About What Every Progra This makes the paper essential for anyone involved in: Concurrent memory access patterns reduce delays by simultaneously accessing different memory banks.

Graphs have been used to keep the text from evince be advised that hyperlinks are used extensively being as dry as it would otherwise be. It is also possible to attach a Southbridge to each node, equally distributing the load on the FSB of all the nodes.