IC 74173 DATASHEET PDF

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Clearing is enabled by taking the clear input to a logic. When both Data Enable Controls datashheet low, data at the D inputs are loaded into the flip—flops with the rising edge of the Clock input.

During normal operation of the device, the outputs of the D flip—flops appear at these dagasheet. Clearing is enabled by taking the clear input to a logic high level.

During 3—state operation, these outputs assume a high— impedance state.

If either of the 2 774173 disables are taken to a logic high level, the Q outputs are fed back to the inputs. The 3-state outputs allow the. The outputs are placed in the 3-stage mode when either of the. When either or both of the.

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74173 PDF Datasheet浏览和下载

A high level on this pin resets all flip—flops and forces the Q outputs low, if they are not already in high—impedance state. A high level on this pin resets all.

When either M or N or both is are high the output is disabled to the high-impedance state. Output Datashet Control inputs. Data on these pins, when enabled by the Data—Enable Controls, are entered into the flip—flops on the rising edge of the clock. The 3-state outputs allow the device to be used in bus organized systems.

Output Enable Controls are high, the Q outputs of the device. Enable Controls are low, data at the D inputs are loaded into. Home – IC Supply – Link. During normal operation of the. Data—Enable Controls, are entered into the flip—flops on the.

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The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. Data on these pins, when enabled by the.

When either or both of the Output Enable Controls are high, the Q outputs of the device are in the high—impedance state.

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Active—low Data Enable Control inputs. The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. When either or both of these controls are high, there is no change in the state of the flip—flops, ddatasheet of any changes at the D or Clock inputs. The data outputs change state on the positive going edge of the clock.

When either M or N or both is are high the output is disabled to the high-impedance state; however sequential datasheef of the flip-flops is not affected.

If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. When both controls are low, the device outputs display the data in the flip—flops. When both controls are.

The four D type Flip-Flops operate synchronously from dtaasheet common clock. During 3—state operation, these outputs assume a high—.